1. Field of the Invention
The invention relates in general to data memory circuits, and relates in particular to a device for definition of the waiting time to be complied with after a storage operation.
2. Description of the Related Art
Digital data memory circuits contain a large number of addressable memory cells, an instruction decoding device for decoding external instructions, and a control device for controlling or initiating operations for operation of the memory circuit, in each case as a function of the decoded instructions. The operation of a data memory circuit includes, in particular, the writing and reading of data to and from selectively addressed memory cells. In principle, a write access or read access comprises a data link being set up between the respectively addressed memory cells and the data connections of the memory circuit, which normally comprises the closing of selected electronic switches in a network of control and data lines which covers the entire array of memory cells. Each write or read process comprises a sequence of individual operations and, in the case of most conventional memory circuits, the relevant operation instructions are applied by an external controller. In general, the controller “knows” the specification of the memory circuit and is thus from the start approximately “aware” of how long it will take to carry out an operation instruction and how long it must in consequence wait until it may send a new instruction which ends the already instructed operation.
However, it is possible for the controller not to be matched exactly to the specification of the memory circuit, and to send a new instruction too early. In this case, the new instruction must not be followed, at least not when the previous operation is “critical” in the sense that its early termination would lead to errors in the subsequent operation, or even to permanent errors in the memory content. Furthermore, in some memory circuits, there are certain operating procedures which are initiated by the controller by an instruction, and then take place as an internally controlled sequence of operations. In this case as well, it is necessary to wait for successful completion of an operation before the next operation is initiated internally.
If the successful completion of an operation cannot be detected and signaled (or if such detection and signaling would be too complex or time-consuming), it is expedient to use a timer which is triggered by the initiation of a “critical” operation and allows a subsequent operation to be started or initiated after a defined time interval. This is conventional in DRAM modules, to be precise particularly for definition of the waiting time “tRAS” between the start of an operation of access to addressed cells and a subsequent reset operation, as explained in the following text.
In the case of conventional DRAM modules, the memory cells within individual fields or segments are each arranged in rows and columns in the form of a matrix. Each cell has an associated control line, which is referred to as a “word line”, and each column has an associated sense line, which is referred to as a “bit line”, which normally has two cores and leads to an amplifier which is associated with the relevant column. These amplifiers are referred to as “read amplifiers” or “sense amplifiers”, although they amplify not only data to be read but also data to be written. Access to a cell is started by activation of the relevant word line on the basis of a row address, as a result of which, the switches at all of the cells in the associated row are closed (that is to say they are switched on) in order to connect these cells via the bit lines to the read amplifiers. In detail, the charge in the cells is dissipated onto the bit lines during this process, which until then have been applied to a common “precharge potential”. The discharging of the cell charge results in the potential on one of the bit line cores rising or falling in each case with respect to the other bit line core, which remains at the precharge potential. The read amplifiers detect the respective potential differences on the bit line pairs and amplify these differences, so that the bit line core with the lower potential is changed to the “low” (earth) potential “L”, and the bit line core with the higher potential is changed to the “high” supply potential “H” of the memory cell array. This results in the information sensed at the cells being written back to the cells in an amplified form, and thus being refreshed.
During an actual read or write operation, following the activation process described above, the read amplifiers are selectively connected, under the control of column address information, to the data connections of the DRAM module. During reading, the data which is “latched” (that is to say held) in the read amplifiers is tapped off at the data connections; for writing, the data which is held in the read amplifiers is overwritten with the new data entered at the data connections, and is thus transmitted via the bit lines to the memory cells.
The entire process of word line activation and amplification by the read amplifier takes a certain minimum amount of time, which is described by the specification parameter tRAS. If a wait for this time is not introduced, for example as a result of a subsequent “precharge” operation being started too early (that is to say the precharging of the bit lines), data losses can occur. In order to preclude this risk, a tRAS timer is activated on word line activation, which does not allow the precharge to be carried out, or does not initiate it, until the full charge state of the cells has been produced.
In the case of the conventional devices, the tRAS timer which is arranged in the DRAM module is an analogue timer, whose delay time is governed by the time constant of an RC circuit. Fluctuations in process parameters during the production of the module and fluctuations in parameters such as the temperature and voltage during operation of the module can lead to fluctuations both in the actual tRAS time in the memory cell array and in the actual delay time of the tRAS timer. For this reason, this timer has in the past been designed with a lead time which takes account of the worst case, that is to say it guarantees that its delay time at the lower end of its possible fluctuation range is still greater than the longest possible actual tRAS time.
This technique has the disadvantage that the tRAS timer is virtually never optimally matched to the instantaneous conditions. Because of the lead time that has been mentioned, the delay time of the timer is in most actual situations considerably longer than the actual tRAS time, so that the precharge operation is delayed further than would actually be necessary. This is at the expense of the operating speed of the DRAM module.
The activation process as described above in a DRAM module is just an illustrative example of processes or operations which are intended to take place in a data memory and must not be terminated or interfered with at any time by the initiation of a subsequent operation. The types of operation in question here depend on the respective type of data memory circuit, as do the waiting times which must be complied with between which operations. If timers similar to the tRAS timer as described above are used in order to comply with the respective waiting times, this results in the same disadvantages as above.